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10 Papers found for "Memory Technology (10)"

High performance data aware (HPDA) SRAM cell for IOT applications

Ajay Kumar Singh, C. M. R. Prabhu, Sargunam T. G.

ARPN Journal of Engineering and Applied Sciences | 2019

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Reliable data aware SRAM cell using FinFET technology

A. K. Singh, C. M. R. Prabhu, Sargunam T. G.

ARPN Journal of Engineering and Applied Sciences | 2019

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A fully differential read-decoupled 7-T SRAM cell to reduce dynamic power consumption

Shahnawaz Arif, Soumitra Pal

ARPN Journal of Engineering and Applied Sciences | 2015

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Design of auto-gated flip -flops based on self gated mechanism

A. Sathya, S. Sangeetha

ARPN Journal of Engineering and Applied Sciences | 2015

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Survey on cache memory design techniques for low power high performance processor

M.Manoranjani, R. Ramya, T. Ravi

ARPN Journal of Engineering and Applied Sciences | 2015

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Leakage reduction using power gating techniquesin SRAM sense amplifiers

Deepak Mittal, Vigneswaran T.

ARPN Journal of Engineering and Applied Sciences | 2015

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A design of SRAM structure for low power using heterojunction CMOS with single bit line

G. Indumathi, M. Ramesh, V.P.M.B. Aarthi alias Ananthakirupa

ARPN Journal of Engineering and Applied Sciences | 2015

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Variation-tolerant sub-threshold SRAM cell design technique

Aminul Islam, Malreddy Shekar Reddy, Soumitra Pal

ARPN Journal of Engineering and Applied Sciences | 2015

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Design of low power high speed DRAM architecture using dual edge triggered flip flop

Manoranjitham M, Vijayashaarathi S

ARPN Journal of Engineering and Applied Sciences | 2015

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Differential 10T TCAM with parallel Pai-sigma matchline

Meenakshi V, Sulthana A

ARPN Journal of Engineering and Applied Sciences | 2015

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