DefinePK

Abstract

Low power and high performance static random access memory (SRAM) are the main key issues and has become vital components in modern VLSI systems. The system power, performance and reliability can be significantly improved by controlling the power dissipation in SRAM. In this paper, the new technique is introduced in the High Performance Data Aware (HPDA) SRAM design to reduce the power dissipation and access delay for read/write operation. The proposed new technique employed in the HPDA SRAM cell has proved to minimize the write power dissipation about 83% and read power consumption about 50%than the 6T cell. The read access time and stability of the HPDA cell are also improved in the new design SRAM cell.