DefinePK

Abstract

Radiation hardening by design has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets, and single event transients are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this work. Temporal hardening mitigates both SEUs and SETs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. In this paper presents an innovative, D Flip-Flop in CMOS design. TheFlip-Flop physical design is laid out in the nm process in the form of an interleaved multi-bit cell and the circuitry necessary for the Flip-Flop to be hardened against SETs and SEUs is analysed with simulations verifying these claims. Comparisonare made to an unhardened D Flip-Flop through speed, size, and power consumption depicting how our technique used increases all three over an unhardened Flip-Flop. Finally, the blocks from both hardened and unhardened Flip-Flop being placed in work and run in 4-bit counter design flows which are compared through size and speed to show the effects of using the high density multi-bit layout.