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Title: Survey on cache memory design techniques for low power high performance processor
Authors: R. Ramya, T. Ravi, M.Manoranjani
Journal: ARPN Journal of Engineering and Applied Sciences
Publisher: Khyber Medical College, Peshawar
Country: Pakistan
Year: 2015
Volume: 10
Issue: 7
Language: English
Cache memory is a additional and fast memory unit that has to be placed between the processing unit and the physical memory. The most recently used instructions and data, where this information are needed to be accessed again are stored in cache .The use of cache memory makes the processing to be faster. As the cache memory moves away from the CPU, the access time and the size of the cache memory storage unit increase as well. The physical memory and external disk storage devices can be accessed faster by the internal registers and cache which are located near to CPU. Cache which are accessed faster and also with less miss rate can be considered to be more power efficient. On-chip caches which are of large size are used in order to overcome cache miss are increasingly used by the modern processors. Also, with each CMOS technology generation, the leakage power consumption is said to be increasing for the past few decade. For this reason, cache power management has become a very important scenario in modern processor design. To address this challenge and also sustainable computing goals are met by several energy efficient techniques that are proposed for the cache architecture. The static and dynamic power consumption will lead to the total power consumption. The power consumption of set associative cache due to access of every cache is more when compared to the direct mapping method, this includes both the tag and the data parameter of the cache. This paper presentsa review on different cache technique and the cache optimization parameters and there are different low power techniques for low power cache.
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