DefinePK

Abstract

The low power and high performance Static Random Access Memory (SRAM) is the main constraint in modern VLSI systems. The SRAM cell power dissipation can be controlled to improve the system power, performance and reliability at a significant level. This research proposes a new technique of Reliable Data Aware (RDA) SRAM cell design using 14 nm FinFET technology to minimize the power dissipation, access delay for read and write operations and maximize the read stability. The proposed FinFET based SRAM design has been employed in RDA SRAM cell and the results analysis proved that the write power dissipation has reduced to 90.14% and read power is about 49.94% than the 6T cell. The read access time and stability of the suggested RDA cell have been improved.