DefinePK

Abstract

At present SRAM cell is under renovation stage. Researchers are trying to propose an SRAM cell that withstands the ever-increasing PVT (process, voltage and temperature) variations and supports low-voltage operation even under subthreshold regime. In this article, a 10T SRAM cell based on DSBB and DTMOS techniques is proposed. This cell is identical to conventional 10T (CON10T) SRAM cell except the body bias connections of the FETs used in the design. This cell is operated in subthreshold region varying from 400 mV to 200 mV. The proposed cell offers 2.64× higher read current and 1.36× tighter spread in read current. It takes 38.04% shorter time to sense a particular data available at the storage nodes with 50.58% improvement in its distribution. The proposed cell benefits 19.48% of write delay and 3.33× tighter spread in write delay compared with its conventional counterpart. It also offers 2× improvement in its write-ability and 2.67× increment in read current to leakage current ratio (IREAD/ILEAK) with same RSNM (105 mV) and hold power (1.17 nW) @ 400 mV.