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Abstract

The highlighted concept of this paper is to employing body bias concept in the design of 16 bit SRAM Array to operate the circuit for low voltage power supply and for achieving low power consumption and consequently reducing transistor count the GDI (Gate Diffusion Input) technique is adopted. By adopting GDI Technique design complexity levels also reduced. By utilizing Dynamic threshold logic and GDI Logic for SRAM cell design to effectively reduce static power dissipation and propagation delays compared to the resistive load inverter being used in previous designs. Peripheral components such as row decoder, precharge circuit, sense amplifier and column decoder has been designed and assembled to form SRAM array using Cadence (version 6.1.5) simulation tool. Standard UMC180 library is used for designing. Supply voltage of0.4V is considered. Transient responses for read and write operations for both logic-1 and logic-0 have been analyzed with operating Frequency 25MHz and the access time for read and write operation is 10ns. Power consumption of 101uW is measured for complete SRAM array.