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Analysis of dynamic power consumption in 4 TAP fir filter using SL based adder and multiplier circuits

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Title: Analysis of dynamic power consumption in 4 TAP fir filter using SL based adder and multiplier circuits

Authors: K. Nehru, Chicle Gopi Bhagya Lakshmi, K. Priyanka, P. Udaya Netha

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2017

Volume: 12

Issue: 20

Language: English

Categories
VLSI (15) Electrical Engineering (5972) Signal Processing (1285) Digital Filters (2) Low Power Design (37)

Abstract

This paper presents the 4 TAP finite impulse responses filter using Shannon based adder cell and multiplier circuit. The basic element of data path system is filters. The data path system involves adder, multiplier and memory element. The 4 TAP filter reports 3.41% improvement in switching power consumption. This circuit is analyzed using spice software with 130 µm technology. The proposed 4 TAP filter is important component of many applications like signal processing and cryptography.

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