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Design and performance evaluation of hybrid GDI logic based adder cells

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Title: Design and performance evaluation of hybrid GDI logic based adder cells

Authors: Suberna S., Vanitha R., Ravi T., Mathan N.

Journal: ARPN Journal of Engineering and Applied Sciences

HEC Recognition History
Category From To
Y 2023-07-01 2024-09-30
Y 2022-07-01 2023-06-30
Y 2021-07-01 2022-06-30
X 2020-07-01 2021-06-30

Publisher: Khyber Medical College, Peshawar

Country: Pakistan

Year: 2017

Volume: 12

Issue: 19

Language: English

Categories
Adders (5) GDI Logic (1) Computer Engineering (1270) VLSI Design (122) Low Power Design (37)

Abstract

This paper deals with the design of full adder using complementary metal oxide semi conductor (CMOS) logic, gate diffusion input (GDI) logic, modified GDI and transmission gate logic. These designs are implemented using H-Spice software. Performance parameters such as power dissipation and transistor counts are compared with the existing designs such as CMOS logic, GDI logic, and modified GDI logic. This design works efficiently with less transistor count and less power dissipation at 130nm technology.

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