DefinePK

Abstract

Present day mobile communication devices equipped with large capacity memories in order to fulfill all the multimedia needs of customers. Now a days, design engineer mainly concentrating not only to equip high capacity memories, but also high bandwidth and low power consuming memories. This paper presents a low power structure for an SRAM cell by modifying the Multi-threshold CMOS architecture. Multi-threshold CMOS architecture is a technique in which transistors with different threshold voltages are used to reduce power consumption and also to reduce delay. This paper presents a more interesting method to reduce power consumption by reducing leakage current in idle condition. This method depicts how the voltage, temperature and transistor size effecting the power consumption in an SRAM cell. This paper presents a novel architecture for SRAM cell to reduce power consumption in the memory structure. SRAM cell is designed with 45 nm technology and is compared with standard 6T SRAM structure. Simulation results shows that power consumption reduced to around 21% when compared with standard 6T SRAM structures.