DefinePK

Abstract

In this paper, we propose an improved 11-T full adder circuit design for minimum power consumption. A novel adder cell is designed with new top-down approach using total number of 11 transistors, thereby, known as 11-T cell. After simulation of the circuit, a clear view of the circuit performance is studied. The proposed adder circuit is compared with reported cells and observed consumed lower in power consumption. The proposed cell gives faster response for the carry output and can be used at higher temperature with minimal power loss. The drawback of the circuit is that it occupies larger area on the chip.