DefinePK

Abstract

In the last decade, the development of embedded on-chip SRAM memories has been radically increasing. The demand of on-chip processing and computations of data in wireless sensor networks (WSN) and Internet-of-Things (IoT) applications have been consistently increasing. This increased requirement influences the embedded on-chip Static Random Access (SRAM) memory to be vital and constantly improve the performance, stability and energy efficiency. The low power, high-performance and energy efficient SRAM has become a very important component in modern systems. In this research work, a Novel Low Power (NLP) FinFET based SRAM cell with 10T is proposed. The proposed cell is designed using 14 nm FinFET technology to reduce the power, read/write delay and improve the stability. The NLP cell has minimized 40% write power and 50% read power. In addition, 50% average delay has improved for write operations and 40% delay for read operations. The NLP cell is proved to be stable in worse conditions with temperature ranging from -50°C to 140°C and works for various VDD starting from 0.8V to 0.25V. Overall, the speed and stability have also improved in read operations due to three transistors. The read stability is improved 2.86x than the conventional cell because of the separate read circuit. The proposed NLP SRAM cell has also improved the read/write stability against the PVT (process, voltage, temperature) variations. It is also observed that the cell has 33.33% area overhead compared to 6T SRAM Cell.