DefinePK

Abstract

An efficient high performance 64-bit MAC unit (Multiplier-and-Accumulator) is presented. In most of the applications Multiplier and Accumulator plays an important role. The existing method is designed using Braun, dadda, etc., like different multiplier architecture and compared the performance of MAC unit with those multipliers. Hence it is vital to design a high-performance multiplier to meet the needs like high speed, less delay, low cost and reduced power. Therefore the proposed method is 64-bit MAC unit which is designed using Vedic multiplier using URDHVA-TIRYAKBHYAM sutra. The main objective of this work was to get an efficient MAC unit with less delay and reduced power. Hence the MAC unit is analyzed using XILINX ISE 13.2 in Verilog HDL and simulated using MODELSIM SE 6.3g and QUARTUS II 9.0.